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(R)
TDA7421
AM/FM TUNER FOR CAR RADIO AND Hi-Fi APPLICATIONS
FRONT-END FOR AM/FM RECEIVERS UP-CONVERSION ARCHITECTURE FOR AM HIGH SPEED PLL WITH INLOCK DETECTOR FOR OPTIMIZED RDS APPLICATIONS SINGLE FREQUENCY REFERENCE FOR AM/FM AM/FM STATION DETECTOR P-CONTROLLED COMPENSATION OF EXTERNAL COMPONENTS SPREAD ADJUSTABLE AUDIO MUTE FULLY PROGRAMMABLE BY I2C BUS ADVANCED BICMOS TECHNOLOGY GENERAL DESCRIPTION The TDA7421 is a high performance tuner circuit that integrates AM/FM sections, IF counter and PLL synthesizer on a single chip. Use of BICMOS technology allows the implementation of tuning functions with a minimum of external components. Value spread of external components can be fully PINS CONNECTION
AM AGC1 RF AMP FM IF AMP1 OUT FM IF AMP1 IN + FM IF AMP2 IN + FM IF AMP1 IN AM AGC1 PIN
TQFP64 ORDERING NUMBER: TDA7421
compensated by means of on-chip electrical adjustment controlled by external P. The Automatic Gain Control (AGC) operates on different sensitivities and bandwidths in order to improve sensitivity and dynamic range. I2C bus allows to control selected functions of the tuner (AGC and amplifiers gain, PLL and counters operation modes).
AM AGC1 TC
MIX OUT +
MIX OUT -
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AM MIX1 IN AM MIX1 IN + FM MIX IN FM MIX IN + FM RF AGC IN FM AGC OUT RF GND VCO B VCO E OSC GND XTAL D XTAL G OSC VCC FM ANT ADJ FM RF ADJ PLL VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DIG GND IFC SSTOP AM STEREO OUT CLN GND IF2 GND AM AGC2 TC PLL GND PLL VREF DIG VDD AM DET SLEEP SDA LP OUT LP IN1 LP IN2 LP IN3 SCL
FM IF AMP2 IN -
AM MIX2 OUT +
AM MIX2 OUT -
FM IF AGC IN
AM MIX2 IN +
AM MIX2 IN-
RF VCC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
FM IF AMP2 OUT IF1 VCC FM LIM IN + FM LIM IN IF1 GND FM BW TC FM MUTE DRIVE FM SMETER AM SMETER FM DET ADJ FM SD AM SD AUDIO OUT FM QUAD+ FM QUADIF2 VCC AM IF2 IN AM REF AM BPF
D96AU546A
June 1998
1/38
MIX OUT-
MIX OUT+
FM IF AGC IN
FM IF AMP1 IN-
FM IF AMP1 IN+
FM IF AMP1 OUT
FM IF AMP2 IN-
FM IF AMP2 IN+
FM IF AMP2 OUT
LIM IN-
LIM IN+
VCO
AM IF2 IN
AM IFREF
AM AGCI TC
AM MIX2 IN-
AM MIX2 OUT-
AM MIX2 IN+
AM MIX2 OUT+
AM BPF
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IFC SSTOP AM STEREO OUT QUAD+ QUADFM MUTE AM IF FM AGC AM IF COUNT FM IF COUNTER AM AM SMETER FM SMETER FM DET ADJ OUT QUADRATURE DETECTOR FM AUDIO OUT FILTER ADJ. SLIDER LIMITER STOP STATION S METER DETUNING DETECTOR SOFT MUTE DETUNING MUTE FM SD AM SMETER AM SD/ FM SD AM SD BW TC TRIPLE OUT
TDA7421
BLOCK DIAGRAM
FM AGC OUT
FM RF AGC IN
FILTER ADJ.
FM MIX IN+
FM MIX IN-
/
PHASE COMPARATOR
VCOE ADJACENT CH. MUTE
VCOB 10.25MHz OSC ADJACENT CH. DET.
XTALG
/
LPIN2 LPIN1 LPIN3
XTALD
/
4 BIT DAC
+
4 BIT DAC
FM ANT ADJ
+
AM MIX INAM RF AGC LOCK DET CHARGE PUMP
FM RF ADJ LPOUT
-
+
AM MIX IN+ FILTER ADJ.
PLL VCC PLL VREF
AM AGC1 RF AMP OUT PLL GND AM IF AGC
AGC1 ANT
SDA SCL SLEEP I2C BUS
AM IF COUNTER
/
AM DETECTOR
AM AGC2 TC
AM DET
D96AU540A
TDA7421
ABSOLUTE MAXIMUM RATINGS
Symbol Tamb Tstg VCC VDD Parameter Operating Temperature Range Storage Temperature Range Analog Supply Voltages (PLL, RF, IF1, IF2, OSC) Digital Supply Voltage Value -40 to 85 -55 to 150 10.2 5.5 Unit C C V V
THERMAL DATA
Symbol Rth j-amb Parameter Thermal resistance Junction-Ambient typ. Value 68 Unit C/W
PIN DESCRIPTION
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name AM MIX1 IN AM MIX1 IN + FM MIX IN FM MIX IN + FM RF AGC IN FM AGC OUT RF GND VCO B VCO E OSC GND XTAL D XTAL G OSC VCC FM ANT ADJ FM RF ADJ PLL VCC LP OUT LP IN1 LP IN2 LP IN3 PLL VREF PLL GND SLEEP SDA SCL Function Input "-" to the AM 1st mixer (differential input) Input "+" to the AM 1st mixer (differential input) Input "-" to the FM mixer (differential input) Input "+" to the FM mixer (differential input) Input to the RF AGC circuit Voltage output to the FM AGC RF circuits ground Local oscillator input to the transistor base (two-pin oscillator) Local oscillator input to the transistor emitter (two-pin oscillator) Oscillator ground Crystal oscillator input to MOS drain (two-pin oscillator) Crystal oscillator input to MOS gate (two-pin oscillator) Oscillator positive supply Tuning varicap voltage for antenna FM filter Tuning varicap voltage for RF FM filter PLL positive supply Op Amp output to PLL loop filters PLL "N. 1" loop filter connection to Op Amp inverting input PLL "N. 2" loop filter connection to Op Amp inverting input PLL "N. 3" loop filter connection to Op Amp inverting input Voltage reference to Op Amp noninverting input PLL ground I2C bus disconnect signal I2C bus data I2C bus clock
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TDA7421
PIN DESCRIPTION (continued)
N. 27 28(*) 29 30 31 32 33 34 35 36 37 38 39 40 (*) 41(*) Name DIG GND IFC SSTOP AM STEREO OUT CLN GND IF2 GND AM AGC2 TC AM DET AM BPF AM REF AM IF2 in IF2 VCC FM QUOD FM QUAD + AUDIO OUT FM SD AM SD FM SMETER AM SMETER FM DET ADJ FM MUTE DRIVE FM BW TC IF1 GND FM LIM IN FM LIM IN + IF1 VCC FM IF AMP2 OUT FM IF AMP2 IN FM IF AMP2 IN + FM IF AMP1 OUT FM IF AMP1 IN FM IF AMP1 IN + AM MIX2 OUT AM MIX2 OUT + RF VCC AM MIX2 IN AM MIX2 IN + FM IF AGC IN MIX OUT MIX OUT + AM AGC1 TC AM AGC1 RF AMP AM AGC1 PIN Digital circuits ground Search stop signal or Output (single ended) of AM IF amplifier "Clean" ground IF 2nd ground AM 2nd AGC time constant Connection to the capacitor of the AM diode-capacitor detector Connection to the AM IF filter Reference voltage of AM IF amplifier Input (single ended) of AM 2nd IF amplifier IF 2nd positive supply "-" Insertion pt. of FM quadrature network (differential) "+" Insertion pt. of FM quadrature network (differential) Audio frequency output (single ended) FM Station detector output or AM Station detector output FM S-meter output or AM S-meter output or FM detuning adjustment FM mute time constant FM detuning detector time constant IF 1st ground Input "-" of FM limiter (differential input) Input "+" of FM limiter (differential input) IF 1st positive supply Output (single ended) of the FM IF 2nd amplifier buffer Input "-" of the FM IF 2nd amplifier (differential input) Input "+" of the FM IF 2nd amplifier (differential input) Output (single ended) of the FM IF 1st amplifier buffer Input "-" of the FM IF 1st amplifier (differential input) Input "+" of the FM IF 1st amplifier (differential input) Output "-" of the AM 2nd mixer (differential output) Output "+" of the AM 2nd mixer (differential output) RF stage positive supply Input "-" to the AM 2nd mixer (differential input) Input "+" to the AM 2nd mixer (differential input) Input FM IF AGC circuit Output "-" of the FM/AM 1st mixer (differential output) Output "+" of the FM/AM 1st mixer (differential output) AM 1st AGC time constant Voltage output of the AM 1st AGC, to the transistor of the RF AF amplifier Current output of the AM 1st AGC, to the PIN diodes antenna AM attenuator Function
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
(*) Pin function is user-defined by software.
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TDA7421
ELECTRICAL CHARACTERISTICS DC PARAMETERS (Tamb = 25C; Vcc = 8.5V, Vdd = 5V unless otherwise specified)
Symbol DIG Vdd DIG Idd PLL VCC PLL ICC RF VCC RF ICC IF1 VCC IF1 ICC IF2 VCC IF2 ICC OSC VCC OSC ICC TOTAL ICC Parameter Digital Supply Voltage Digital Supply Current PLL Supply Voltage PLL Supply Current RFSupply Voltage RF Supply Current IF1 Supply Voltage IF1 Supply Current IF2 Supply Voltage IF2 Supply Current Oscillator Supply Voltage Oscillator Supply Current Total Supply Current AM MODE FM MODE AM MODE FM MODE AM MODE FM MODE AM MODE FM MODE AM MODE FM MODE AM MODE FM MODE AM MODE FM MODE Test Condition Min. 4.75 4.0 3.5 7.5 1.2 2.5 7.5 15.0 10.0 7.5 2.2 16.0 7.5 8.5 27.0 7.5 14.5 11.0 45.0 73.0 4.6 4.0 1.6 3.0 17.5 13.0 2.7 19.5 10.5 32.0 17.0 14.0 50.0 81.0 Typ. Max. 5.25 5.2 4.5 10 2.0 3.5 10 20.0 16.0 10 3.2 23.0 10 12.5 37.0 10 19.5 17.0 55.0 89.0 Unit V mA mA V mA mA V mA mA V mA mA V mA mA V mA mA mA mA
AC PARAMETERS Ref: FM Test Circuit measure Vosc with high impedance FET probe Voltage Controlled Oscillator (VCO)
Symbol fVCOmin fVCOmax VOSC Parameter Minimum VCO Frequency Maximum VCO Frequency Oscillator Amplitude Test Condition Vturn = 0, Europe/USA Japan Vturn = VCC, Europe/USA Japan fosc = 108.8MHz, Europe/USA fOSC = 72.3MHz, Japan 123.2 79.2 Min. Typ. 80.9 55 128 90 106 Max. 98.2 65.4 Uni MHz MHz MHz MHz dBu
Reference Oscillator Ref: AM Test Circuit measure VXTAL with high impedance FET probe
Symbol fXTAL VXTAL Parameter Reference Frequency Oscillator Amplitude Test Condition Min. Typ. 10.25 108 Max. Uni MHz dBu
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) FM Section Global Performances Refer to Evaluation Circuit and enclosed curves (S+N/N, THD) - RF Input: fc = 98.1MHz, 75KHz dev., 1KHz mod.,60dBu - Audio Output: BPF 20Hz - 20KHz
Symbol S+N/N THD VO AF US AGCrange Parameter Signal to Noise Ratio Total Harmonic Distortion Audio Output Level Usable Sensitivity Range AGC FM deviation = 40KHz 350 antenna level at which S+N/N=30dB 65 Test Condition Min. Typ. 68 0.3 400 4 450 Max. Uni dB % mVRMS dBu dB
FM Front-end Electrical Adjustments Ref: FM Test Circuit measure VANTADJ and VRFADJ referred to VPLLOUT
Symbol ANTADJ
MAX OFF
Parameter Maximum FM Antenna Filter Adjustment Voltage Offset FM Antenna Filter Adjustment Voltage Offset Step Maximum FM RF Filter Adjustment Voltage Offset FM RF Filter Adjustment Voltage Offset Step
Test Condition VPLLOUT = 2.5V, ANA3-0 set to 1111 VPLLOUT = 2.5V, ANA3-0 set to 1001 VPLLOUT = 2.5V, RFA3-0 set to 1111 VPLLOUT = 2.5V, RFA3-0 set to 1001
Min. 21 2.8 21 2.8
Typ. 25 3.6 25 3.6
Max. 27 4.4 27 4.4
Uni % % % %
ANTADJ
STEP OFF
RFADJ
MAX OFF
RFADJ
STEP OFF
FM Mixer Ref: FM Test Circuit, measure input at VMIXFMIN, output at VMIXOUT
Symbol ZIN,MIX GMIX IP3MIX CP1MIX Parameter Single-ended input impedance (pin 3, pin4) Conversion Gain 3rd order intermodulation distortion intercept point 1dB compression point Test Condition f = 100MHz fIN = 98.1MHz fd = 98.1MHz; fu1 = 98.2MHz; fu2 = 98.3MHz; fIN = 98.1MHz Min. Typ. 12 21.8 104 90 Max. Unit dB dBu dBu
FM AGC Ref: FM Test Circuit, measure input at VFMRFAGCIN, and VFMIFAGCIN, output at VFMAGCOUT
Symbol VRFAGCSTART Parameter Open Loop Rf Agc Starting Point Test Condition fRFAGCIN = 98.1MHz Value of VFMRFAGCIN, at which VFMAGCOUT = 4V fIFAGCIN = 10.7MHz Value of VFMIFAGCIN, at which VFMAGCOUT = 4V FAGC2-0 set to 111 Min. 74 Typ. 80 Max. 86 Unit dBu
RINRFAGC VIFAGCSTART
Input Resistance Open Loop If Agc Starting Point
20 71 77 83
K dBu
RINIFAGC ROUTFMAGC
Input Resistance Output Resistance
20 10
K K
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) FM IF Amplifier 1 Ref: FM Test Circuit, measure input at VFMAMP1IN, output at VFMAMP1OUT
Symbol RIN,AMP1 ROUT,AMP1 GTYP,AMP1 GMIN,AMP1 GMAX,AMP1 IP3AMP1 CP1AMP1 Parameter Input Resistance Output Resistance Typical Gain Minimum Gain Maximum Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Test Condition f = 10.7MHz f = 10.7MHz fIN = 10.7MHz, FBH3-0 set to 0100 fIN = 10.7MHz, FBH3-0 set to 0001 fIN = 10.7MHz, FBH3-0 set to 0000 fd = 10.7MHz; fu1= 10.8MHz; fu2= 10.9MHz, FBH3-0 set to 0100 fIN = 10.7MHz; FBH3-0 set to 0100 Min. Typ. 330 330 17.5 15.5 19.5 109 96 Max. Unit dB dB dB dBu dBu
16.5 14.5 18.5
18.5 16.5 20.5
FM IF Amplifier 2 Ref: FM Test Circuit, measure input at VFMAMP2IN, output at VFMAMP2OUT
Symbol RIN,AMP2 ROUT,AMP2 GTYP,AMP2 GMIN,AMP2 GMAX,AMP2 IP3AMP2 CP1AMP2 Parameter Input Resistance Output Resistance Typical Gain Minimum Gain Maximum Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Test Condition f = 10.7MHz f = 10.7MHz fIN = 10.7MHz, FBL3-0 set to 0100 fIN = 10.7MHz, FBL3-0 set to 0001 fIN = 10.7MHz, FBL3-0 set to 0000 fd = 10.7MHz; fu1= 10.8MHz; fu2= 10.9MHz, FBL3-0 set to 0100 fIN = 10.7MHz; FBL3-0 set to 0100 Min. Typ. 330 330 6 4 8 122 110 Max. Unit dB dB dB dBu dBu
5 3 7
7 5 9
FM Limiter, Field Strengh Meter and Demodulator Ref: FM Test circuit, measure: - Input at VFMLIMIN, fIN = 10.7MHz - filtered FS Meter output at VSM,FILT - shifted FS Meter output at VSM,SHIFT (FMADJ set to 0) - demodulator adjustment output at VSM,SHIFT (FMADJ set to 1)
Symbol RIN,LIM GLIM LS SM1 SM2 SM3 SMMINSHIFT SMMAXSHIFT GDEM GDEMADJ Parameter Limiter Input Resistance Limiter Gain Limiting Sensitivity Smeter 1 at VSM,FILT Smeter 2 at VSM,FILT Smeter 3 at VSM,FILT Smeter Minimum Shift Voltage at VSM,SHIFT referred to VSM,FILT Smeter Maximum Shift Voltage at VSM,SHIFT referred to VSM,FILT Demodulator Conversion Gain Demodulator Adjustment Conversion Gain Test Condition Min. Typ. 330 90 23 0.25 2.75 4.35 0.3 1.8 2 14 Max. Unit dB dBu V V V V V mVRMS/ KHz mVRMS/ KHz
VFMLIMIN = VFMLIMIN = VFMLIMIN = VFMLIMIN = 00000 VFMLIMIN = 11111 VFMLIMIN >
42dBu 77dBu 102dBu 70dBu, FSL4-0 set to 70dBu, FSL4-0 set to LS
0.1(1) 2.4(1) 4.0(1) 0.25 1.55
0.5(1) 3.1(1) 4.7(1) 0.35 2.05
VFMLIMIN > LS, measured at VSMSHIFT, FMADJ set to 1
NOTE1: Refer to Global application circuit; input at first Ceramic Filter in, FBH3-0 set to 0001, FBL3-0 set to 0001
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) FM Audio Amplifier Ref: FM Test circuit, measure: - Input at VFMLIMIN, = 95dBu, fIN = 10.7MHz - audio output at VAUDIO, BPF 20Hz to 20KHz - muting voltage at VMUTE, DRIVE
Symbol VMUTE Parameter Mute Voltage Test Condition VMUTE,DRIVE for which VAF = 29dB, FMHIGH set to 0, AUM2-0 set to 111 VMUTE,DRIVE for which VAF = 1dB, FMHIGH set to 0, AUM2-0 set to 111 VMUTE,DRIVE < VPLAY VMUTE,DRIVE > VMUTE, FMHIGH set to 1, AUM2-0 set to 001 VMUTE,DRIVE > VMUTE, FMHIGH set to 0, AUM2-0 set to 111 fDEV = 75KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE fDEV = 75KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE fDEV = 75KHz, FMOD = 1KHz, VMUTE,DRIVE < VMUTE AM modulation deph 30%, fMOD = 1KHz, with respect to FM modulated signal with fDEV = 40KHz, VMUTE,DRIVE < VMUTE Min. 2 Typ. Max. Unit V
VPLAY
Play Voltage
0.3
V
Audio Amplifier Gain in Play Conditions GAMP,MUTEMAX Audio Amplifier Highest Gain in Mute Condition GAMP,MUTEMIN Audio Amplifier Lowest Gain in Mute Condition VAF AF Output Level GAMP,PLAY THD S+N/N AMR AFTotal Harmonic distortion AF Signal to Noise Ratio Amplitude Modulation Rejection
9 6.5 -21 350(1) 400 0.5 68(1) 60(1) 75 67
dB dB dB 450(1) mVRMS % % dB
AUDIOcurr MUTE Rout
Audio Out Current Capability Mute Drive Output Resistance
5 1
mA K
NOTE1: Refer to Global application circuit; input at first Ceramic Filter in, FBH3-0 set to 0001, FBL3-0 set to 0001
FM QUALITY DETECTORS Field Strength Detector Ref: FM Test Circuit, measure: - Input at VFMLIMIN, fIN = 10.7MHz, CW - output at VMUTE,DRIVE
Symbol FSDMIN Parameter Field Strenght Detector Minimum Threshold Field Strenght Detector Maximum Test Condition VFMLIMIN level at which VMUTE,DRIVE = VMUTE, FSM3-0 set to 0000 VFMLIMIN level at which VMUTE,DRIVE = VMUTE, FSM3-0 set to 1111 Min. Typ. 40 Max. Unit dBu
FSDMAX
60
dBu
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) Detuning Detector Ref: FM Test Circuit, measure: - Inputs at VFMLIMIN, CW - output at VMUTE,DRIVE
Symbol DDSTART DDSLOPE,MIN Parameter Detuning Detector Starting Point Detuning Detector Minimum Muting Slope Test Condition frequency shift from 10.7MHz at which VMUTE,DRIVE = VPLAY frequency shift from 10.7MHz + DDSTART, at which VMUTE,DRIVE = VMUTE, BWM2-0 set to 100, FMRECSEEK set to 0 frequency shift from 10.7MHz + DDSTART, at which VMUTE,DRIVE = VMUTE, BWM2-0 set to 001, FMRECSEEK set to 0 ratio of "reception" mode integration time constant inside the Detuning Detector with respect to "seek" mode Min. Typ. 23 30 Max. Unit KHz KHz
22.5
37.5
DDSLOPE,MAX Detuning Detector Maximum Muting Slope
7.5
10
12.5
KHz
DDTRC
Detuning Detector Time Constant Ratio
34/6
s/s
Adjacent Channel Detector Ref: FM Test Circuit, measure: - Inputs at VFMLIMIN: desired 10.7MHz, 95dBu CW; undesired 10.8MHz CW - output at VMUTE,DRIVE - BWM2-0 set to 001
Symbol ACDMAX Parameter Adjacent Channel Quality Detector Maximum Sensitivity Threshold Adjacent Channel Quality Detector Minimum Sensitivity Threshold Test Condition amplitude of undesired signal at which VMUTE,DRIVE = VMUTE, HDM4-0 set to 11111 amplitude of undesired signal at which VMUTE,DRIVE = VMUTE, HDM4-0 set to 00000 Min. Typ. 91 Max. Unit dBu
ACDMIN
94.8
dBu
Field Strength Station Detector Ref: FM Test Circuit, measure: - Inputs at VFMLIMIN: desired 10.7MHz, CW - output at VFMSD - FMRECSEEK set to 1
Symbol FSSDMIN FSSDMAX Parameter Field Strength Station Detector Minimum Threshold Field Strength Station Detector Maximum Threshold Test Condition VFMLIMIN level at which VFMSD = 2.5, FSM4-0 set to 00000 VFMLIMIN level at which VFMSD = 2.5, FSM4-0 set to 11111 Min. Typ. 24 76 Max. Unit dBu dBu
Detuning Station Detector Ref: FM Test Circuit, measure: - Input at VFMLIMIN, CW; - output at VFMSD - FMRECSEEK set to 1
Symbol DSD Parameter Detuning Station Detector Threshold Test Condition frequency shift from 10.7MHz at which VFMSD = 2.5V Min. Typ. 23 Max. Unit KHz
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) Adjacent Channel Station Detector Ref: FM Test Circuit, measure: - Input at VFMLIMIN: desired 10.7MHz, 95dBu CW; undesired 10.8MHz CW - output at VFMSD - FMRECSEEK set to 1
Symbol ACSDMAX Parameter Adjacent Channel Detector Maximum Sensitivity Threshold Adjacent Channel Detector Minimum Sensitivity Threshold Test Condition amplitude of undesired signal at which VFMSD = 2.5V, HDM4-0 set to 11111 amplitude of undesired signal at which VFMSD = 2.5V, HDM4-0 set to 00000 Min. Typ. 92.5 Max. Unit dBu
ACDMIN
94.9
dBu
AM Section Global Performances Refer to Evaluation Circuit and enclosed curves (S+N/N, THD) - RF Input: fc = 1MHz, f mod = 1KHz, m = 0.3; - Audio Output: BPF 20Hz - 20KHz
Symbol VIN MIN VIN US Vis S+N/N IMAG Tw THD Parameter Maximum Sensitivity Usable Sensitivity AGC Range Signal to Noise Ratio Image Rejection Tweet Total Harmonic Distortion Test Condition VINRF = 74dBu; VAF = - 20dB S+N/N = 20dB VINRF = 74dBu; VAF = -10dB VINRF = 74dBu f1 = 1.9MHz f2 = 22.4MHz VINRF = 74dBu; f1 = 900KHz; f2 = 1350KHz VINRF = 74dBu; m = 0.3 VINRF = 74dBu; m = 0.8 VINRF = 120dBu; m = 0.3 VAF VAMST Audio Output Level AM IF2 Output level VINRF = 74dBu VINRF = 74dBu 137 46.0 Min. Typ. 20 31 50 53.0 Max. Unit dBu dBu dB dB dB 1.2 0.45 1.73 0.33 167 106 197 1.0 dB % % % mVRMS dBu
AM Mixer 1 Ref: AM Test Circuit, measure input at VMIX2AMIN, output at VMIXOUT
Symbol RINMIX1 GMIX1 IP3MIX1 CP1MIX1 Parameter Input Resistance Conversion Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Test Condition fIN = 1MHz fd = 1MHz; fu1 = 1.1MHz; fu2 = 1.2MHz; fIN = 1MHz Min. 7.5 Typ. 1.2 8.5 115 98.7 Max. 9.5 Unit K dB dBu dBu
10/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued) AM Wide & Narrow AGC Ref: AM Test Circuit, input at VMIX1AMIN, and VMIX2AMIN, output at VAMAGC1AMP, andVAMAGC1PIN
Symbol VWAGCTYP Parameter Open Loop WIDE AGC Typical Starting Point Open Loop WIDE AGC Minimum Starting Point Open Loop WIDE AGC Maximum Starting Point Open Loop NARROW AGC Typical Starting Point Open Loop NARROW AGC Minimum Starting Point Open Loop NARROW AGC Maximum Starting Point Output Resistance Maximum Pin-diode Current fWAGCIN = 1MHz; VMIX1AMIN = 90dBu; AAG3-0 set to 0000 Test Condition fWAGCIN = 1MHz, AAG3-0 set to 1000; VMIX1AMIN at which VAMAGC1AMP = 2.5V fWAGCIN = 1MHz, AAG3-0 set to 0000; VMIX1AMIN at which VAMAGC1AMP = 2.5V fWAGCIN = 1MHz, AAG3-0 set to 1111; VMIX1AMIN at which VAMAGC1AMP = 2.5V fNAGCIN = 10.7MHz, AAG3-0 set to 1000; VMIX2AMIN at which VAMAGC1AMP = 2.5V fNAGCIN = 10.7MHz, AAG3-0 set to 0000; VMIX2AMIN at which VAMAGC1AMP = 2.5V fNAGCIN = 10.7MHz, AAG3-0 set to 1111; VMIX2AMIN at which VAMAGC1AMP = 2.5V Min. Typ. 91.3 Max. Unit dBu
VWAGCMIN
80.6
dBu
VWAGCMAX
95.6
dBu
VNAGCTYP
93.2
dBu
VNAGCMIN
82.8
dBu
VNAGCMAX
97.4
dBu
ROUTAMAGC1 IAMAGC1PIN
23.3 1.4
K mA
AM Mixer 2 Ref: AM Test Circuit, measure input at VMIX2AMIN, output at VMIX2OUT, (switches must be in position 2 for AGC measurements).
Symbol RINMIX2 GMIX2 IP3MIX2 CP1MIX2 AGCMIXCP Parameter Input Resistance Maximum conversion Gain 3rd Order Intermodulation Distortion Intercept Point 1dB Compression Point Central Point of AGC2 Intevention on Mixer 2 AGC2 Starting Point on Mixer 2 Test Condition fIN = 10.7MHz fd = 10.7MHz; fu1 = 10.8MHz; fu2 = 10.9MHz; fIN = 10.7MHz fIN = 10.7MHz; VMIX2AMIN = 52dBu; Value of VMIX2OUT fIN = 10.7MHz; Value of VMIX2AMIN for which VMIX2OUT is AGCMIXCP 3dB fIN = 10.7MHz; Range of VMIX2AMIN for which VMIX2OUT is AGCMIXCP 3dB Min. Typ. 5 19.6 122 90.7 61.2 Max. Unit K dB dBu dBu dBu
AGCMIXSP
40
dBu
AGCMIXR
AGC2 Range on Mixer 2
24
dB
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TDA7421
ELECTRICAL CHARACTERISTICS (continued) AM IF2 Amplifier Ref: AM Test Circuit, measure input at VIP2AMPIN, output at VIP2AMPOUT, (switches must be in position 1), fIN = 450KHz.
Symbol RIN,IF2AMP GIF2AMP AGCAMPCP AGCAMPSP AGCAMPR Parameter Input Resistance Maximum Gain Central Point of AGC2 Intevention on IF2 Amp AGC2 Starting Point on IF2 Amp AGC2 Range on IF2 Amp Test Condition VIF2AMPIN = 10dBu VIF2AMPIN = 72dBu; Value of VIF2AMPOUT Value of VIF2AMPIN for which VIF2AMPOUT is AGCAMPCP - 3dB fIN = 10.7MHz; Range of VMIX2AMIN = for which VMIX2OUT is AGCMIXCP 3dB Ratio of AGC2 "reception" Time Constant and "seek" Time Constant VIF2AMPIN = 72dBu; AMSTEREO set to 1 AMSTEREO set to 1 Min. Typ. 2 51 115 63 36 Max. Unit K dB dBu dBu dB
AGCTCR IFAMST IFAMSTcurr
AGC2 Time Constant Ratio AM IF2 Output Level at pin 28 Current Capability of pin 28
150/5 104 106 150 108
s/s dBu A
AM Field Strength Meter and Field Strength Station Detector Ref: AM Test Circuit, measure at VMIX2AMIN, outputs at VAMSMETER and at VAMSD (switches in position 2), - fIN = 10.7KHz. - AMSEEK set to 1
Symbol AMSM1 AMSM2 AMSM3 AMSDMIN AMSDMAX Parameter AM Smeter 1 at VAMSMETER AM Smeter 2 at VAMSMETER AM Smeter 3 at VAMSMETER Station Detector Minimum Threshold Station Detector Maximum Threshold Test Condition VMIX2AMIN = 35dBu VMIX2AMIN = 65dBu VMIX2AMIN = 95dBu VMIX2AMIN at which VAMSD = 2.5V, ASS3-0 set to 0000 VMIX2AMIN at which VAMSD = 2.5V, ASS3-0 set to 1111 Min. 2.2 2.5 3.0 Typ. 2.89 3.26 3.73 44 64 Max 3.6 4.0 4.5 Unit V V V dBu dBu
IF Counter Output Ref: AM & FM Test Circuit, measure at pin 28
Symbol IFCFM Parameter FM IFC Sensitivity Test Condition VFMLIMIN at which Vpin 28 = 2.5V, FMRECSEEK set to 1, EW2-0 set to 101, IFS2-0 set to 010 VIF2AMPIN at which Vpin 28 = 2.5V, AMSEEK set to 1, EW2-0 set to 011, IF2-0 set to 100, AMFM STBY1-0 set to 10 Min. Typ. 34 Max Unit dBu
IFCAM
AM IFC Sensitivity
29
dBu
IFCcurrent
IFC Current Capability
150
A
12/38
TDA7421
ELECTRICAL CHARACTERISTICS (continued) Loop Filter Input Output (LP_IN1, LP_IN2, LP_IN3, LP_OUT)
Symbol -IIN IIN VOL VOH IOUT IOUT Parameter Input Leakage Current Input Leakage Current Output Voltage Low Output Voltage High Output Current Sink Output Current Source Test Condition VIN = GND; PDout = Tristate 1) VIN = VDD; PDout = Tristate IIN = -0.2mA; VCC = 8.5V IOUT = 0.2mA; VCC = 8.5V VPLL = 8.5V; Vout = 0.5 to 8V 8 10 10 Min. -2 -2 Typ. 0 0 Max. 2 2 0.5 Unit A A V V mA mA
I2C Bus Interface
Symbol fSCL tAA tbuf tHD-STA tLOW tHIGH tSU-SDA tHD-DAT tSU-DAT tR tF tSU-STO tDH VIL VIH Parameter SCL Clock Frequency SCL Low to SDA Data Valid Time the Bus Must Be Free for the New Transmission START Condition hold Time Clock Low Period Clock High Period Start Condition Setup Time Data Input Hold Time Date Input Setup Time SDA & SCL Rise Time SDA & SCL Full Time Stop Condition Setup Time DATA OUT Time Input Low Voltage Input High Voltage 4.7 300 1 3 Test Condition Min. Typ. 100 300 4.7 4.0 4.7 4.0 4.7 0 250 Max 500 Unit KHz ns s s s s s s ns s s s ns V V
(1) depends upon filter circuitry (2) depends upon application circuit (3) depends only upon IF2 ceramic filter
13/38
TDA7421
AM TEST CIRCUIT
VMiXOUT 1 330
VAMAGC1RFAMP
2 2K
T2 VCC
VMiX2AMIN
T3 VCC
64
IAMAGC1PIN
63
61
60
58
57
55
54
AGC W&N 1 VMIX1AMIN 2 1 VIF2AMPIN
2 2K
35 34
15pF
+ 11 1M
-
VXTAL
AGC2 12 40 VAMSD 41 VAMSMETER
DET
33
VIF2AMPOUT
15pF
31
32
D97AU803A
FM TEST CIRCUIT
VMIXOUT
VFMAMP1IN
330 VFMIFAGCIN
VFMAMP1OUT
VFMAMP2IN
VFMAMP2OUT
T2 VTun VCC
10nF 10nF 10nF 10nF
330 10nF 10nF
10nF
330
VMiXFMIN
T1 1:3.5
3
61
60
59
53
52 330 +
51
50 330
49
48 330 + 46 10nF VFMLIMIN 10nF
330 VTun 5K V1 L2 4
22pF
15pF
8 9 330 45
1.8K
68pF
+
VFMRFAGCIN VFMAGCOUT 10nF 14 VAMTADJ 15 VRFADJ 16 VPLLOUT 40 VFMSD 41 VSMSHIFT 10nF 5 6 FM AGC AUDIO
-
38 DEMOD L6 37
39 VAUDIO 100K
42 VMUTEDRIVE 10nF
31 VSMFILT
D97AU804A
14/38
TDA7421
FM SECTION Featuring a single conversion configuration, it comprises a multi-stage IF limiter whose gain is I2C controlled and a quadrature demodulator with detuning and adjacent channel detectors. Signal meter and stop station functions are also supported AM SECTION AM signal is converted by means of UP-DOWN configuration (IF1 = 10.7MHz, IF2 = 450KHz) and MW/LW bands are covered. PLL SECTION Three operating modes are available:
PM0 0 1 0 1 PM1 0 0 1 1 Operating Mode Standby AM not used FM
by A0, A1, A2 registers for high current and B0, B1 registers for low current. LOW NOISE CMOS OP-AMP An internal voltage divider at pin VREF connects the positive input of the low noise Op-Amp. The charge pump output connects the negative input. This internal amplifier in cooperation with external components can provide an active filter. The negative input is switchable to three input pins (LPIN 1, LPIN 2 and LPIN 3), to increase the flexibility in application. This feature allows two separate active filters for different applications. A logical "1" in the LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the high current mode is activated LPIN 3 is switched on. INLOCK DETECTOR The charge pump is switched in low current mode as the truth table and the related figure shows.
CURRHIGH 0 1 1 1 1 LOCKENA X 1 1 0 0 LOCK (by inlock detector) X 1 0 1 0 Charge Pump Current low current low current High current High current High current
They are user programmable with the mode PM registers. Standby mode It stops all functions. This allows low current consumption without loss of information in all registers. The pin LP-OUT is forced to 0V in power on. All data registers are set to FE (11111110). The oscillator runs even in stand-by mode. FM and AM Operation The FM or AM signal applies to a 32/33 prescaler, which is controlled by a 5 bit counter (A). The 5 bit register (PC0 to PC4) controls this divider. The output of the prescaler connects to a 11 bit divider (B). The 11 bit register (PC5 to PC15) controls the divider 'B'. THREE STATE PHASE COMPARATOR The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator. CHARGE PUMP CURRENT GENERATOR This stage generates signed pulses of current. The phase error signal decides the duration and polarity of those pulses. The current absolute values are programmable
The charge pump is forced in low current mode when a phase difference of 10-40 usec is reached. A phase difference larger than the programmed values will switch the charge pump immediately in the high current mode. Few programmable delays are available for inlock detection. IF COUNTER SYSTEM FOR AM/FM The IF counter mode is controlled by IFCM register:
IFCM1 0 0 1 1 IFCM0 0 1 0 1 FUNCTION NOT USED FM MODE AM MODE NOT USED
A sample timer to generate the gate signal for the main counter is built with a 14 bit programmable counter to have the possibility to use any fre-
15/38
TDA7421
ADDRESS ORGANIZATION (PLL and IF Counter)
MSB FUNCTION PLL CHARGE PUMP PLL COUNTER PLL COUNTER PLL REF COUNTER PLL REF COUNTER PLL LOCK DETECT IFC REF COUNTER IFC REF COUNTER IFC CONTROL IFC CONTROL SUBAD 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H BIT 7 L P IN 1 / 2 PC7 PC15 RC7 RC15 LDENA IRC7 IFCM1 IFENA IFS2 BIT 6 CURRH PC6 PC14 RC6 RC14 IRC6 IFCM0 IFS1 BIT 5 B1 PC5 PC13 RC5 RC13 D3 IRC5 IRC13 IFS0 BIT 4 B0 PC4 PC12 RC4 RC12 D2 IRC4 IRC12 CF4 BIT 3 A3 PC3 PC11 RC3 RC11 D1 IRC3 IRC11 CF3 BIT 2 A2 PC2 PC10 RC2 RC10 D0 IRC2 IRC10 EW2 CF2 BIT 1 A1 PC1 PC9 RC1 RC9 PM1 IRC1 IRC9 EW1 CF1 LSB BIT 0 A0 PC0 PC8 RC0 RC8 PM0 IRC0 IRC8 EW0 CF0
quency. In FM mode a 6.25 KHz, in AM mode a 1KHz signal is generated. This counter is followed by an asynchronous divider to generate several sampling times. Intermediate Frequency Main Counter (IFMC) This counter is a 13-21 bit synchronous autoreload down-counter. Four bits are programmable to have the possibility for an adjust to the frequency of the IF filter. The counter length is automatically adjusted to the chosen sampling time and the counter mode. At the start the counter will be loaded with a defined value which is an equivalent to the divider value (tsample fIF). If a correct frequency is applied to the IF counter frequency inputs IF-AM and IF-FM, at the end of the sampling time the main counter is changing its state from 0 to 1FFFFFH. This is detected by a control logic. The frequency range inside which a successful count results is detected is adjustable setting bits EW 0, 1, 2. Up-down counter filter The information coming from the IF main counter control logic is shifted into a 5 bit up down counter circuit clocked by the sampling time signal. At the start (rising edge of the IFENA signal) the counter is set to 10H and the SSTOP signal is forced to "1". Only when the counter reaches the value 10H step, SSTOP goes to "0". SSTOP will be "1" again, if the counter reaches the value 10h + step.
Charge Pump Logic
CURR HIGH CHARGE PUMP CURRENT LOCKENA
LOCK
D96AU548
FM and AM operation (swallow mode)
I2C bus
REF OSC IN
fosc
REGISTER R0 ...R15 DIVIDER :R I C bus
2
fref fsyn
PD
REGISTER PC0 ...PC4 COUNTER A (O/I) PRESCALER 32/33 FM IN
2 I C bus
AM IN
REGISTER PC5 ... P15 DIVIDER :B
D96AU545
16/38
TDA7421
ttim = (IFRC + 1) / fosc tcnt = (CF + 1697) / fIF tcnt = (CF + 44) / fIF Counter result succeeded: ttim > tcnt - terr and ttim > tcnt + terr
FM mode AM mode
by controlling the discrimination window. This is adjustable by programming the control registers EW0...EW2. The measurement time per cycle is adjustable by setting the register IFS0 - IFS2. The center frequency of the discrimination window is adjustable by the control register "CF0" to "CF4". The available values are reported in databyte specification I2C BUS INTERFACE General Description The TDA7421 supports the I2C bus protocol. This protocol defines the devices sending data into the bus as transmitter and the receiving device as the receiver. The device that controls the transfer is a master and the device being controlled is the slave. The master will always initiates data transfer and provide the clock to transmit or receive operations. Data Transition Data transition on the SDA line must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as START or STOP condition. Start Condition
Counter result failed: ttim< tcnt + terr or ttim > tcnt - terr where: ttim = IF time cycle time tcnt = IF counter cycle time terr = discrimination window (controlled by the EW registers)
succeeded tcnt -tERR tcnt +tERR
D96AU551
failed
failed
ttim
The precision of the measurements is adjustable Phase Comparator
17/38
TDA7421
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level. This START condition must precede any command and initiate a data transfer onto the bus. The TDA7421 continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this condition has not been met. Stop condition A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH level. This condition terminate the communication between the devices and force's the bus interface of the TDA7421 into the initial condition. Acknowledge Indicates a successful data transfer. The transmitter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it has received the eight bits of data correctly. Data transfer During data transfer the TDA7421 samples the SDA line on the leading edge of the SCL clock, Therefore, for proper device operation the SDA line must be stable during the SCL LOW to HIGH transition. Device Addressing To start the communication between two devices, CONTROL REGISTER FUNCTION
REGISTER NAME PC RC IRC IFCM EW IFENA CF IFS PM D LPIN1/2 A B LDENA CURRH
the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6 bits of the slave address identify the device type. The TDA7421 device code is fixed as "110001". The next significant bit is used either to address the tuner section (1) or the PLL section (0) of the chip. Following a START condition the master sends slave address word; the TDA7421 will "acknowledge" after this first transmission and wait for a second word (the word address field). This 8 bit address field provides an access to any of the 8 internal addresses. Upon receipt of the word address the TDA7421 slave device will respond with an "acknowledge". At this time, all the following words transmits to the TDA7421 will be considered as data. The internal address will be automatically incremented. After each word receipt the TDA7421 will answer with an "acknowledge". The interface protocol comprises: - a subaddress byte - a sequence of data (N-bytes + acknowledge) - a stop condition (P) - a start condition (S) - a chip address byte
FUNCTION Programmable Counter for VCO Frequency Reference Counter PLL Reference Counter IF IF Counter Mode Frequency Error Window Enable IF Counter Center Frequency IF Counter Sampling Time IF Counter Stby, FM, AM, AM swallow mode (PLL Mode) Programmable Delay for Lock Detector Loop Filter Input Select Charge Pump High Current Charge Pump Low Current Lock Detector Enable Set Current High
18/38
TDA7421
IF Counter Block Diagram
IFENA EW-REGISTER
IF-AM
11-21 BIT COUNTER
ZD
IF-FM
CF-REGISTER
UP/DOWN COUNTER
OSC
14 BIT COUNTER
3 BIT COUNTER
IFC-REGISTER
IFS-REGISTER
D97AU809
I2C Bus Timing Diagram
tHIGH tR tLOW tR
SCL
tSU-STA tHD-DAT tHD-STA tSD-DAT tSUBTOP
SDA IN
tAA tDH ttxt
SDA OUT
D95AU378
19/38
TDA7421
Frame Example For addressing the PLL part:
CHIP ADDRESS MSB S 1 1 0 0 0 1 0 LSB 0 ACK MSB T2 T1 T0 I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA 1 to DATA n LSB ACK P
D96AU549
for the TUNER part:
CHIP ADDRESS MSB S 1 1 0 0 0 1 1 LSB 0 ACK MSB 0 0 0 I SUBADDRESS LSB A3 A2 A1 A0 ACK MSB DATA 1 to DATA n LSB ACK P
D96AU550
ACK = Acknowledge S = Start P = Stop TUNER SUBADDRESS
MSB X X X I A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0
I = Page mode T2, T1, T0 = used in test mode (for PLL only, for TUNER addressing they must be 0) A3, A2, A1, A0 = Mode selection
LSB A0 0 1 0 1 0 1 0 1 0 1
FUNCTION STATUS FM STOP STATION / FM IF AGC FM SMETER SLIDER AM AGC1 / AM STOP STATION IFT1 / IFT2 FRONT END ADJUSTMENT FM DEMODULATOR ADJUSTMENT FM IF BUFFERS FM AUDIO MUTE GAIN / FM SOFT MUTE FM HOLE DETECTOR / FM DETUNING Page mode disabled Page mode enabled must be "0"
0 1 0 0 0
PLL SUBADDRESS
MSB T3 T2 T1 I A3 0 0 0 0 0 0 0 0 1 1 A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 LSB A0 0 1 0 1 0 1 0 1 0 1 FUNCTION Charge pump control PLL counter 1 (LSB) PLL counter 2 (MSB) PLL reference counter 1 (LSB) PLL reference counter 2 (MSB) PLL lockdetector control and PLL mode select IFC reference counter 1 (LSB) IFC reference counter 2 (MSB) and IFC mode select IF counter control 1 IF counter control 2 page mode DISABLED page mode enabled
0 1
T1, T2, T3 are used for testing the PLL, in application mode they have to be "0".
20/38
TDA7421
PLL DATA BYTE SPECIFICATION CHARGEPUMP CONTROL
MSB D7 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION High current = 0mA High current = 0.5mA High current = 1.0mA High current = 1.5mA High current = 2.0mA High current = 2.5mA High current = 3.0mA High current = 3.5mA High current = 4.0mA High current = 4.5mA High current = 5.0mA High current = 5.5mA High current = 6.0mA High current = 6.5mA High current = 7.0mA High current = 7.5mA Low current = 0A Low current = 15A Low current = 100A Low current = 115A Select low Current Select high Current Select loop filter 1 Select loop filter 2 Subaddress = 00H
D6
D5
D4
D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 0 1 1 0 1 0 1 LPIN1/2 CURRH
0 1 0 1
B1
B0
A3
A2
A1
A0
PLL COUNTER 1 (LSB)
MSB D7 0 0 0 1 1 1 1 PC7 D6 0 0 0 1 1 1 1 PC6 D5 0 0 0 1 1 1 1 PC5 D4 D3 D2 D1 0 0 1 0 0 1 1 PC1 0 0 0 0 0 0 0 0 0 all combinations allowed 1 1 1 1 PC4 1 1 1 1 PC3 1 1 1 1 PC2 LSB D0 0 1 0 0 1 0 1 PC0 LSB = 0 LSB = 1 LSB = 2 *** LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 01H FUNCTION
21/38
TDA7421
PLL COUNTER 2 (MSB)
MSB D7 0 0 0 1 1 1 1 PC15 D6 0 0 0 1 1 1 1 PC14 D5 0 0 0 1 1 1 1 PC13 D4 0 0 D3 0 0 D2 0 0 D1 0 0 1 0 0 1 1 PC9 LSB D0 0 1 0 0 1 0 1 PC8 MSB = 0 MSB = 256 MSB = 512 *** MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name Subddress = 02H FUNCTION
0 0 0 all combinations allowed 1 1 1 1 PC12 1 1 1 1 PC11 1 1 1 1 PC10
Swallow mode: fvco/fsyn = LSB + MSB + 32
PLL REFERENCE COUNTER 1 (LSB)
MSB D7 0 0 0 1 1 1 1 RC7 D6 0 0 0 1 1 1 1 RC6 D5 0 0 0 1 1 1 1 RC5 D4 0 0 D3 0 0 D2 0 0 D1 0 0 1 0 0 1 1 RC1 LSB D0 0 1 0 0 1 0 1 RC0 LSB = 0 LSB = 1 LSB = 2 *** LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress =03H FUNCTION
0 0 0 all combinations allowed 1 1 1 1 RC4 1 1 1 1 RC3 1 1 1 1 RC2
PLL REFERENCE COUNTER 2 (MSB)
MSB D7 0 0 0 1 1 1 1 RC15 D6 0 0 0 1 1 1 1 RC14 D5 0 0 0 1 1 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 0 0 1 1 RC9 LSB D0 0 1 0 0 1 0 1 RC8 MSB = 0 MSB = 256 MSB = 512 *** MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name FUNCTION
all combinations allowed 1 1 1 1 1 1 1 1 RC12 1 1 RC11 1 1 RC10
1 1 RC13
Subddress = 04H
fOSC/fREF = LSB + MSB + 1
22/38
TDA7421
LOCK DETECTOR & PLL MODE CONTROL
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 LDENA D3 D2 D1 D0 PM1 PM0 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 FUNCTION PLL standby mode PLL AM not used PLL FM mode PD phase difference threshold 10ns PD phase difference threshold 20ns PD phase difference threshold 30ns PD phase difference threshold 40ns Not used in application mode Activation delay = 4 fref Activation delay = 6 fref Activation delay = 8 fref No lock detector controlled chargepump Lock detector controlled chargepump Bit name Subaddress = 05H
IF COUNTER REFERENCE CONTROL 1 (LSB)
MSB D7 0 0 0 1 1 1 1 IRC7 D6 0 0 0 1 1 1 1 IRC6 D5 0 0 0 1 1 1 1 IRC5 D4 D3 D2 D1 0 0 1 0 0 1 1 IRC1 0 0 0 0 0 0 0 0 0 all combinations allowed 1 1 1 1 IRC4 1 1 1 1 IRC3 1 1 1 1 IRC2 LSB D0 0 1 0 0 1 0 1 IRC0 LSB = 0 LSB = 1 LSB = 2 *** LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 06H FUNCTION
23/38
TDA7421
IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 1 1 1 0 0 1 1 0 1 0 1 IRC12 IRC11 IRC10 IRC9 IRC8 D4 0 0 D3 0 0 D2 0 0 D1 0 0 1 0 1 1 LSB D0 0 1 0 1 0 1 MSB = 0 MSB = 256 MSB = 512 *** MSB = 15616 MSB = 15872 MSB = 16128 NOT USED IN APPLICATION MODE IF counter FM mode IF counter AM mode not used Bit name Subaddress = 07H FUNCTION
0 0 0 all combinations allowed 1 1 1 1 1 1 1 1 1
IFCM1 IFCM0 IRC13
fosc/ftim = LSB + MSB + 1 IF COUNTER CONTROL 1
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 1 IFENA EW2 EW1 EW0 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 don't use don't use don't use EW delta f = 6.25KHz (FM); 1KHz (AM) EW delta f = 12.5KHz (FM); 2KHz (AM) EW delta f = 25KHz (FM); 4KHz (AM) EW delta f = 50KHz (FM); 8KHz (AM) EW delta f = 100KHz (FM); 16KHz (AM) IF counter disabled / stand by IF counter enabled Bit name Subaddress = 08H FUNCTION
24/38
TDA7421
IF COUNTER CONTROL 2
MSB D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fcenter = 10.60000MHz (FM) 448KHz (AM) fcenter = 10.60625MHz (FM) 449KHz (AM) fcenter = 10.61250MHz (FM) 450KHz (AM) fcenter = 10.61875MHz (FM) 451KHz (AM) fcenter = 10.62500MHz (FM) 452KHz (AM) fcenter = 10.63125MHz (FM) 453KHz (AM) fcenter = 10.63750MHz (FM) 454KHz (AM) fcenter = 10.64375MHz (FM) 455KHz (AM) fcenter = 10.65000MHz (FM) 456KHz (AM) fcenter = 10.65625MHz (FM) 457KHz (AM) fcenter = 10.66250MHz (FM) 458KHz (AM) fcenter = 10.66875MHz (FM) 459KHz (AM) fcenter = 10.67500MHz (FM) 460KHz (AM) fcenter = 10.68125MHz (FM) 461KHz (AM) fcenter = 10.68750MHz (FM) 462KHz (AM) fcenter = 10.69375MHz (FM) 463KHz (AM) fcenter = 10.70000MHz (FM) 464KHz (AM) fcenter = 10.70625MHz (FM) 465KHz (AM) fcenter = 10.71250MHz (FM) 466KHz (AM) fcenter = 10.71875MHz (FM) 467KHz (AM) fcenter = 10.72500MHz (FM) 468KHz (AM) fcenter = 10.73125MHz (FM) 469KHz (AM) fcenter = 10.73750MHz (FM) 470KHz (AM) fcenter = 10.74375MHz (FM) 471KHz (AM) fcenter = 10.75000MHz (FM) 472KHz (AM) fcenter = 10.75625MHz (FM) 473KHz (AM) fcenter = 10.76250MHz (FM) 474KHz (AM) fcenter = 10.76875MHz (FM) 475KHz (AM) fcenter = 10.77500MHz (FM) 476KHz (AM) fcenter = 10.78125MHz (FM) 477KHz (AM) fcenter = 10.78750MHz (FM) 478KHz (AM) fcenter = 10.79375MHz (FM) 479KHz (AM) tsample = 20.48ms (FM mode); 128ms (AM; MODE) tsample = 10.24ms (FM mode); 64ms (AM; MODE) tsample = 5.12ms (FM mode); 32ms (AM; MODE) tsample = 2.56ms (FM mode); 16ms (AM; MODE) tsample = 1.28ms (FM mode); 8ms (AM;MODE) tsample = 640s (FM mode); 4ms (AM;MODE) tsample = 320s (FM mode); 2ms (AM; MODE) tsample = 160s (FM mode); 1ms (AM; MODE) CF1 CF0 bit name Subaddress = 09H FUNCTION
1 1 0 1 1 1 IFS2 IFS1 IFS0 CF4 CF3 CF2
25/38
TDA7421
TUNER DATA BYTE SPECIFICATION ADDRESS ORGANIZATION (Tuner AM/FM)
MSB FUNCTION STATUS SUBAD 00H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 T ES T O N FMMUTE FMADJ FMHIGH AMSTER AMSEEK AM/FM/ EO / FM STBY RECSEEK FAG2 FSL4 ASS3 T2A3 ANA3 SDD FBL3 FSM3 BWM2 FAG1 FSL3 ASS2 T2A2 ANA2 DEM6 FBL2 FSM2 BWM1 FAG0 FSL2 ASS1 T2A1 ANA1 DEM5 FBL1 FSM2 BWM0 FSS4 FSL1 ASS0 T2A0 ANA0 DEM4 FBL0 FSM0 HDM4 FSS3 FSL0 AAG3 T1A3 RFA3 DEM3 FBH3 HDM3 FSS2 AAG2 T1A2 RFA2 DEM2 FBH2 AUM2 HDM2 FSS1 AAG1 T1A1 RFA1 DEM1 FBH1 AUM1 HDM1 LSB BIT 0 AM/FM/ STBY FSS0 AAG0 T1A0 RFA0 DEM0 FBH0 AUM0 HDM0
FM STOP STATION/ FM IF AGC FM SMETER SLIDER AM AGC1/AM STOP STATION IFT1/IFT2 FRONT END ADJUSTMENT FM DEMODULATOR ADJUSTMENT FM IF BUFFERS FM SOFT MUTE/ FM AUDIO MUTE GAIN FM HOLE DETECTOR /FM DETUNING DETECTOR
01H 02H 03H 04H 05H 06H 07H 08H 09H
26/38
TDA7421
STATUS (subaddress 00H)
MSB S7 S6 S5 S4 S3 S2 S1 TESTON FMMUTE FMADJ FMHIGH AM AM AM/FM/ STEREO SEEK/FM STBY RECSEEK X X 0 X X X X X X 0 1 0 1 X X 0 0 0 0 0 0 LSB S0 AM/FM/ STBY 0 1 1 1 1 1 1 STAND-BY FM ON, RECEPTION, DEEP MUTE FM ON, SEEK, DEEP MUTE FM ON, RECEPTION, SHALLOW MUTE FM ON,SEEK SHALLOW MUTE FM ON FOR DEMOD ADJUSTM, DEMOD ON FM ON FOR DEMOD ADJUSTMENT DEMOD MUTED AM ON (Japan), RECEPTION, IFC OUT SELECTED AM ON (Japan), SEEK, IFC OUT SELECTED AM ON (Japan), RECEPTION AM STEREO OUT SELECTED AM ON (Japan), SEEK, AM STEREO OUT SELECTED AM ON (EU, US), RECEPTION, IFC OUT SELECTED AM ON (EU, US), SEEK, IFC OUT SELECTED AM ON (EU, US), RECEPTION AM STEREO OUT SELECTED AM ON (EU, US), SEEK, AM STEREO OUT SELECTED PLL TEST OUTPUT ENABLED FUNCTION
X 0 0 0 0 0 0
X 0 0 0 0 0 1
X 0 0 0 0 1 1
X 0 0 1 1 X X
0 0 0
X X X
X X X
X X X
0 0 1
0 1 0
1 1 1
0 0 0
0 0 0 0
X X X X
X X X X
X X X X
1 0 0 1
1 0 1 0
1 1 1 1
0 1 1 1
0 1
X
X
X
1
1
1 X
1 X
AM TURN ON SEQUENCE AT POWER ON: it is necessary to cycle through ST-BY for a correct operation.
27/38
TDA7421
FM STOP STATION / FM IF AGC (subaddress 01H)
MSB FAG2 fmifagc MSB FAG1 fmifagc FAG0 fmifagc LSB FAG4 fmstop station MSB 0 X 1 FSS3 fmstop station 0 X 1 FSS2 fmstop station 0 X 1 FSS1 fmstop station 0 X 1 LSB FSS0 fmstop station LSB 0 X 1 FM STOP STATION THRESHOLD Maximum sensitivity *** Minimum sensitivity FM IF AGC THRESHOLD 0 X 1 1 0 X 1 1 0 X 0 1 Maximum sensitivity *** Minimum sensitivity Keying AGC disabled FUNCTION
all combinations allowed
all combinations allowed
FM SMETER SLIDER (subaddress 02H)
MSB FSL4 fmsmeters lider MSB FSL3 FSL2 fmsmeterslider FSL1 FSL0 fmsmeter slider LSB FM SMETER SLIDER THRESHOLD (mV) 300 (baseline) 348.4 (+48.4) 396.8 (+96.8) 493.6 (+193.6) 687.2 (+387.2) 1074.4 (+774.4) 1800 (top) LSB FUNCTION
0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 all combinations allowed
0 1 0 1 0 0 1
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TDA7421
AM STOP STATION / AM AGC1 (subaddress 03H)
MSB ASS3 amstopsta tion MSB ASS2 ASS1 ASS0 amstopsta tion LSB AAG3 amagc1 MSB 0 X 1 AAG2 amagc1 0 X AAG1 amagc1 0 X amstopstation LSB AAG0 amagc1 LSB 0 X 1 AM AGC1 THRESHOLD Maximum sensitivity *** Minimum sensitivity AM STOP STATION THRESHOLD Maximum sensitivity *** Minimum sensitivity FUNCTION
1 1 all combinations allowed
0 X 1
0 X 1
0 X 1
0 X 1
all combinations allowed
IFT1/ IFT2 (subaddress 04H)
MSB T2A3 IFT2 adjust MSB T2A2 IFT2 adjust T2A1 IFT2 adjust T2A0 IFT2 adjust LSB T1A3 IFT1 adjust MSB 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 T1A2 IFT1 adjust 0 0 0 1 0 1 T1A1 IFT1 adjust 0 0 1 0 0 1 LSB T1A0 IFT1 adjust LSB 0 1 0 0 0 1 ADJUSTMENT CAPACITOR 0 Cift1 2Cift1 4Cift1 8Cift1 15Cift1 0 Cift2 2Cift2 4Cift2 8Cift2 15Cift2 FUNCTION
all combinations allowed
1 0 0 0 1 1 all combinations allowed
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FRONT END ADJUSTMENT (subaddress 05H)
MSB ANA3 ant adjustm MSB ANA2 ant adjustm ANA1 ant adjustm ANA0 ant adjustm LSB RFA3 RF adjustm MSB X 0 0 0 0 1 1 1 1 RFA2 RF adjustm 0 0 0 1 1 0 0 1 1 RFA1 RF adjustm 0 0 1 0 1 0 1 0 1 LSB RFA0 RF adjustm LSB 0 1 0 0 1 1 0 0 1 Voffset RF varicap / VPLL 0 -3.6% -7.2% -14.3% -25% 3.6% 7.2% 14.3% 25% V offset antenna varicap / VPLL X 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 -3.6% -7.2% -14.3% -25% 3.6% 7.2% 14.3% 25% FUNCTION
all combinations allowed
all combinations allowed
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TDA7421
FM DEMODULATOR ADJUSTMENT (subaddress 06H)
MSB SDD SD disable DEM6 demadj MSB 0 0 0 0 0 0 0 1 1 DEM5 demadj 0 0 0 0 0 0 1 0 1 DEM4 demadj 0 0 0 0 0 1 0 0 1 DEM3 demadj 0 0 0 0 1 0 0 0 1 DEM2 demadj 0 0 0 1 0 0 0 0 1 DEM1 demadj 0 0 1 0 0 0 0 0 1 LSB DEM0 demadj LSB 0 1 0 0 0 0 0 0 1 ADJUSTMENT CAPACITOR 0 Cdemod 2Cdemod 4Cdemod 8Cdemod 16Cdemod 32Cdemod 64Cdemod 127Cdemod SD DISABLE 0 1 SD ENABLED SD DISABLED (High impedance output) FUNCTION
all combinations allowed
FM IF BUFFERS (subaddress 07H)
MSB FBL3 FBL2 FBL1 FBL0 FBH3 FBH2 FBH1 LSB FBH0 BUFFER 1 GAIN (dB) 19.5 15.5 16.5 17.5 18.5 BUFFER 2 GAIN (dB) 0 0 0 0 1 0 0 0 0 0 1 0 0 0 8 4 5 6 7 FUNCTION
buff2 buff2 gain buff2 gain buff2 gain buff1 buff1 buff1 gain buff1 gain MSB LSB gain MSB gain MSB gain LSB 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0
1 0 0 0 all else not allowed
0 1 1 0 0 0 all else not allowed
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TDA7421
FM SOFT MUTE / FM AUDIO MUTE GAIN (subaddress 08H)
MSB FSM3 FSM2 FSM1 FSM0 AUM2 AUM1 LSB AUM0 FUNCTION FM SOFT MUTE THRESHOLD
fmsoftmute fmsoftmute fmsoftmute fmsoftmute MSB LSB 0 0 0 0 X X X X 1 1 1 1 all combinations allowed
buff1 gain buff1 gain buff1 gain MSB LSB
0 0 1 0 1 1
0 1 0 1 1 1
0 0 1 0 1 1
0 1 0 1 1 1
Maximum sensitivity *** Minimum sensitivity Audio max mute atten. (dB) with bit FMHIGH byte 0 = 1 1 -2.5 0 -5 0 -7.5 1 -10 0 -12.5 1 -15 Audio max mute atten. (dB) with bit FMHIGH byte 0 = 0 1 -17.5 0 -20 0 -22.5 1 -25 0 -27.5 1 -30 all else not allowed
FM HOLE DETECTOR / FM DETUNING DETECTOR (subaddress 09H)
MSB BWM2 BW MSB BWM1 BW BWM0 BW LSB HDM4 Hole det MSB 0 X 1 HDM3 Hole det HDM2 Hole det HDM1 Hole det LSB HDM0 Hole det LSB 0 X 1 MUTING SENSITIVITY Minimum (deep hole) *** Maximum (shallow hole) FUNCTION
0 0 0 X X X 1 1 1 all combinations allowed
RECEPTION 0 0 1 0 1 0 1 0 0 all else not allowed SEEK 0 0 0 X X X 1 1 1 all combinations allowed
DETUNING MUTE RANGE 10 (KHz) 15 (KHz) 30 (KHz) CLAMPING WINDOW Minimal Window Intermediate values Maximal Window
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TDA7421
Evaluation Board Schematic Circuit (part A)
30 dB differential gain
FM IN SP RFVcc
From Cx - see schematic (part D) 100K 0
10n
10n 1 T1 MIX_IN 50 1K 100n 22u + 6p 100K 0 100K 22p 15p 68p 3.3p 0 1K5 1K5 TP20 4.7n 4.7n OSCVcc 5K6 10n 10n + 10u 0 TP21 47n 0 L2 15p 10.25MHz 15p 1M 1K8 470 3p 5p 6p 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AM MIX1 INAM MIX1 IN+ FM MIX INFM MIX IN+ FM RF AGC IN FM AGC OUT RF GND VCO B VCO E OSC GND XTAL D XTAL OSC VCC FM ANT ADJ FM RF ADJ PLL VCC
1K5 From LPOUT - pin 17
Evaluation Board Schematic Circuit (part B)
IFC SSTOP/AM ST
CLN GND
DIG GND
DIG VDD
IF2 GND 30
AM AGC2 TC 31
PLL VREF
PLL GND
LP IN2
17
18
19
20
21
22
23
24
25
26
27
28
29
From Rx 33n 33K 2.7n 4K3 22n 3.3n +
32
AM DET
LP OUT
SLEEP
LP IN1
LP IN3
SDA
SCL
TP18
TP22 4.7n 1n + 2.2u 18K I2CBUS 1 2 3 4 5 22n +5V 10u + TP19 AM ST
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TDA7421
Evaluation Board Schematic Circuit (part C)
see schematic (part D)
TP12
TP11
FMIF AMP2OUT IF1 VCC FM LIM IN+ FM LIM IN-
48 47 46 45 22n 22n 2.2u TP13 TP16 + IF1Vcc 0 0 CF4 10.7MHz 50 FMIF2
IF1 GND 44 43 FM BW TC 42 FM MUTE DRIVE FM/AM S-METER 41 FM SD/AM SD AUDIO OUT FM QUAD+ FM QUADIF2 VCC AM IF2 IN AM REF AM BPF 40 39 38 37 36 35 34 33
+ TP14 TP15 1u 100K
AUDIO OUT 5K6 IF2Vcc
L6
+ 1mH 120p TP17 10n
22u
Evaluation Board Schematic Circuit (part D)
FMIF1 RFVcc 50 27 RFVcc 0 100n 82p AM IN AMAMP 10n 27 50 15p 1u + + 4K7 T2 T3 470 0 0 4K7 1.5n + 1M 1u 68p + 2K7 1u 3p 68uH 0 10n 82p 68uH 120p RFVcc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 10n 49 22n 22n 0 22n 0 0 1 1 TP10 TP9 TP1 1 TP2 1 18p 0 RFVcc 0 F2 450KHz 0 1mH 1K 0 100n CF1 10.7MHz TP3 1 TP4 1 0 0 0 1 TP8 0 50 AMIF TP5 1 TP6 1 TP7 1
0
22n F3 10.7MHz
10n
AM AGC1 RF AMP
AM MIX2 OUT+
FM IF AGC IN
AM MIX2 IN-
FMIF AMP1 IN+
From pin 1 - AM MIX IN-
FMIF AMP1OUT
FMIF AMP2IN+
AM MIX2 OUT-
FMIF AMP1 IN-
FMIF AMP2IN-
AM AGC1 PIN
AM AGC1 TC
AM MIX2 IN+
MIX OUT+
MIX OUT-
RF VCC
From pin 35 - AM IF2 IN From pin 48 - FMIF AMP2 OUT
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TDA7421
Evaluation Board Schematic Circuit (part E)
Supply Voltage (12V) Gnd MR1 +Vs JP1 1 220n + 100u 10 10 10 10 RFVcc PLLVcc OSCVcc IF1Vcc & IF2 Vcc
2 10u + 100n 3
F.C. N.C.
OUT 8.5V 4 GND GND GND GND 100n + 47u 8 7 6 GND GND VIN 220n 5 NC 4 NC L78L05A
+VS
L4916 56 78
1 +5V 220n Ground path
2
GND GND
VO
Notes: - The components shown on the evaluation board schematic without the part value, are required only for measurements between intermediate input/outputs: - Parts description:
CF1 CF3-CF4 CF2
Ceramic filter 10.7MHz, 180KHz BW Ceramic filter 10.7MHz, 150KHz BW Ceramic filter 450KHz, 6KHz BW FM RF transformer Unloaded Q= 103 3-1= 3 1/2T - 6-4= 1T 0.122UEW CTUNING(3-1)= 24pF @ 100MHz AM/FM IF1 transformer Unloaded Q= 70 1-3= 13T - 1-5= 6 1/2T - 5-3= 6 1/2T - 4-6= 2T 0.082UEW CINT(1-2) = CINT(2-3) = 82pF; CEXT(1-3) = 10pF AM IF2 transformer Unloaded Q= 40 1-3= 178T - 1-2= 89T - 2-3= 89T - 4-6= 33T 0.052UEW CINT(1-3) = 180pF; CEXT(1-3) = 20pF Oscillator coil Unloaded Q= 80 6-4= 2 1/2T 0.122UEW CTUNING(6-4)= 36.8pF @ 100MHz Demodulator Coil Unloaded Q= 35 6-4= 27T 0.12UEW CINT(4-6)= 47pF; CEXT(4-6) = 13.5pF
T1
T2
T3
L2
L6
3
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TDA7421
FM THD FM S+N/N
Vs= 8V fin= 98.1MHz +/-75KHz fm= 1KHz RESPONSE (dB) 20Hz - 20KHz filter T.H.D. (%)
Vs= 8V fin= 98.1MHz +/- 75KHz fm= 1KHz 20Hz - 20KHz filter without de-emphasis
FIELD STRENGTH
(dBu)
FIELD STRENGTH (dBu)
AM THD
AM S+N/N
Vs= 8V fin= 1MHz m= 30% fm= 1KHz RESPONSE (dB) 20Hz - 20KHz filter T.H.D. (%)
Vs= 8V
fin= 1MHz m= 30% fm= 1KHz 20Hz - 20KHz filter
FIELD STRENGTH
(dBu)
FIELD STRENGTH (dBu)
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TDA7421
TQFP64 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 0.0157 mm TYP. MAX. 1.60 0.15 1.45 0.28 0.20 0.002 0.053 0.007 0.0047 0.055 0.009 0.0063 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0236 0.0393 0.0295 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 0.0079
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
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TDA7421
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1998 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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